The invention relates to a phase locked loop ("PLL") comprising
a phase comparator having an oscillator input for receiving an oscillator signal and a data input for receiving an input signal comprising pulses, PA1 a loopfilter circuit having an input coupled to an output of said phase comparator, and PA1 an oscillator with a control input coupled to an output of said loopfilter circuit and an output coupled to the oscillator input of the phase comparator, PA1 the phase locked loop further comprising PA1 a frequency deviation detector for detecting a difference in frequency between said data signal and said oscillator signal, the frequency deviation detector having an output coupled to an input of said loop filter circuit. PA1 a pulse length detector for determining the direction for rounding the length of a pulse in said input signal to an integer number of periods of the oscillator signal, said integer number of periods having a total length closest to said length of said pulse. By measuring the length of a pulse in periods of the oscillator signal and detecting if the nearest integer number of periods is smaller or larger than the measured length, each pulse contributes to the frequency deviation signal provided the frequency deviation is relatively modest. In accordance with the invention the pulse length detector may actually calculate the sign of the difference of the pulse length and its nearest integer-number of periods. An alternative, in which the tractional amount is detected by which the length of the pulse exceeds the largest integer number of oscillator periods smaller than the pulse length may be measured. This fractional amount is directly related to the sign and the latter can be derived by determining if said fractional amount is above or below one half. Various other schemes to determine numbers that are directly related to the sign of the rounding operation can be used within the scope of the present invention.
Such a PLL is used for recovery of a clock signal from a digital data signal in which pulses have a length that is an integral multiple of a basic length unit. For example, the data signal from a digital optical read-out apparatus such as a CD-player or other digital recording apparatus. The clock signal is used to derive the length of each pulse as a number of basic length units. Therefore, the oscillator should operate at a frequency such that the oscillator period is locked to the basic length unit as much as possible. Such a PLL can also be used when all the pulses have the same length. The invention also relates to a decoder circuit for a digital recording system comprising such a PLL.
A PLL and a decoder circuit according to the introductory paragraph is known from Philips Data Handbook 1990, Vol IC01a, pages 671-691. In this document a decoder circuit (SAA7210) is described for a digital audio circuit. The circuit includes a PLL with an analog voltage controlled oscillator. When the PLL-system is not phase-locked a capture-aid circuit comprising a pair of frequency deviation detectors generates a signal to pull the oscillator frequency into the capture range of the PLL. In the capture-aid circuit a first frequency detector compares the frequency deviation of the oscillator with that of a crystal clock, providing coarse frequency deviation control. The second frequency detector uses data run length violations to provide fine frequency control. A run length violation occurs when a pulse in the data signal is determined to have a length that does not occur in the signal; the standardized compact disc format EFM-coding (Eight to Fourteen Modulation) pulses have a run length of at least three and at most eleven periods of the basic length unit. Once the PLL is locked a lock detector disables the outputs of the frequency deviation detectors to enable the PLL to operate without being disturbed by spurious signals from the frequency deviation detectors.
This known circuit has as a disadvantage that pulses of shortest or longest possible length may be relatively rare in certain types of coding or data sequences. In EFM coding only 1% of the pulses has the maximum length of eleven basic units. In general the known circuit is sensitive for noise that disturbs the longest length pulses. A consequence of this is that lock-in is poor (slow) with certain types of coding or data sequences, and that the PLL frequency may drift away during a fast jump. On a disc-shaped record carrier a fast jump occurs when the read-out unit makes a fast movement in the radial direction, crossing a number of the circular information tracks. During fast (radial) jump, the PLL will read data only a short time from a certain track. After this time, it will skip to the next track. The crossing of the tracks disturbs the longest pulses in such a way that the capture aid circuit will not pull the PLL frequency to the data frequency any more. Pulses of longest length may not be properly recognized and false detections are possible as well.